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The AIPS ( Artificial Intelligent Partner System ) Home Page 018
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この講義に関する参考文献のLISTです。
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See three invited talks related to SONY HAD sensor now called also as Pinned
Photo Diode.
(1) International Conference CCD79 in Edinburgh, Scotland UK
(2) International Conference ESSCIRC2001 in Vilach, Austria.
(3) International Conference ESSCIRC2008 in Edinburgh, Scotland UK
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Hagiwara was invited in these international conferences because of his
contributions
to the image sensor community and related digital system LSI chip design
works.
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Publication List of Hagiwara Yoshiaki while a PhD student at Caltech.
(1)"The Influence of Interface States on Incomplete Charge
TRansfer in Overlapping Gate Charge-Coupled Devices"
by Amr M.Mohsen, T.C.McGill, Yoshiaki Daimon Hagiwara,
and Carver A. Mead, IEEE Journal of Soild-State Circuits
Vol. SC.8 , No.2, April 1973
(2)"Buried Channel CCD Charge Transfer" by Yoshiaki Hagiwara,
T.C.McGill, and Carver A. Mead, ISSCC1974 Paper
in Philadelphia, USA, February 1974
(3)"Final Stage of the Charge-Transfer Process in Chrge-Coupled
Devices" by Yoshiaki Daimon Hagiwara, Amr M. Mohsen, and
T.C.McGill, IEEE Transactions on Electron Devices, VOl. ED-21,
No.4, April 1974
(4) "128-Bit Mutlicomparator", C.A.Mead, R.D.Pashley, L.D.Brutton,
Yoshiaki Daimon Hagiwara and S.F.Sando, IEEE Journal of
Soild-State Circuits Vol. SC.11 , No.4, October 1976
Publication List of Hagiwara Yoshiaki at Sony
(5)Japanese Patent 1975-127646, filed on October 23, 1975
Invention of the N+NP+NP-P junction type Pinned Photodiode
with the P+NP junction type charge transfer gate to the CTD.
with the back light illumination scheme.
(6)Japanese Patent 1975-127647, filed on October 23, 1975
Invention of the N+NP+N junction type Pinned Photodiode
with the surface MOS type charge transfer gate to the CTD.
with the back light illumination scheme.
(7)Japanese Patent 1975-134985, filed on October 23, 1975
Invention of the P+NPNsub junction type Pinned Photodiode
with the built-in vertical overflow drain (VOD) function
(8) “A 380Hx488V CCD imager with narrow channel transfer gates,”
by Y. Daimon-Hagiwara, M. Abe, and C. Okada, Proceedings of
the 10th Conference on Solid State Devices, Tokyo, 1978, Japanese
Journl of Applied Physics, vol. 18, supplement 18–1, pp. 335–340, 1979.
Hagiwara designed the Frame Transfer CCD image sensor alone with
the homemade design CAD tool that Hagiwara himself built, using FORTAN
programming software and with the company main frame computer.
Abe helped Hagiwara for the CCD chip fabrication.
Okada helped Hagiwara for the CCD chip testing.
Hagiwara was inveited to the internation CCD image sensor conference
to present his work on the P+NP junction photodiode at Edinburgh.
(9) Hagiwara, CCD'79 invited paper on "SONY Image Sensor Efforts"
at Edinburgh, Scotland UK on SONY CCD image sensors.
This is the first paper in the world reporting the P+NP type photodiode
with the Pinned surface potentail and complete charge trasfer to the CTD.
Hagiwara reported a very low dark current, the result of the surface pinning.
This paper is the origin of the SONY HAD(hole accumulation diode and
the Pinned Photodiode. Pinned Photodiode and SONY HAD both have the
pinned surface potential, which is the result of the hole accumulation in
the densely doped surface potential. This P+NP junction type photodiode
is based on the Hagiwara 1975 patent (1975-134985) of the P+NPNsub
junction type photodiode structure with complete charge transfer.
(10) "Interline Transfer CCD image sensor" with tranparent electrode and
complete charge transfer, by Kano, Ando, Matsumoto, Hagiwara and
Hashimoto, Japanese Television Society, Electon Device Reserch Coference,
ED481, pp.47-52, Jan 24, 1980.
Hagiwara designed the Interline Transfer CCD image sensor alone with
the homemade design CAD tool that Hagiwara himself built, using FORTAN
programming software and with the company main frame computer.
Kano and Matumoto helped Hagiwara for the CCD chip fabrication.
Ando and Hashimoto helped Hagiwara for the CCD chip testing.
The two-chip set color video camera was sold to ANA and installed in
the cockpit of the Jumbo 747, introduing to the world a completely
image-lag-free action video camera.
SONY CCD top management people decided to concentrate their dilligence
to the mass production of the Interline Transfer CCD image sensor with
tranparent electrode with the lateral overflow drain.
SONY CCD top management people ignored Hagiwara 1975 patent invention
on the P+NPNsub junction type photodiode, which has a very low dark current
and very high blue light sensitivity, and besides the vertical overflow drain (VOD)
built-in structure can produce extra window area for more light sensitivity.
Hagiwara persistantly talked to SONY CCD top management people, institing that
his invetion of the P+NPNsub junction type photodiode is much better. But SONY
CCD top management people did not listen to Hagiwara. Finally, they fired Hagiwara.
Hagiwara had to move to another project sector and became the leader of a newly
organized Fast SRAM cache memory design team for digital CCD camera system.
Hagiwara and his team published the fast 4 Mega Bit Cache SRAM in ISSCC1989.
(11)Fumio Miyaji, Yasushi Matsuyama, Yoshikazu Kanaishi, Katsunori Senoh,
Takashi Emori and Yoshiaki Hagiwara, "A 25 nanosec 4 Mega bit CMOS
RAM with DYnamic Bot-Line Loads", ISSCC1989 and J.Solid State Circuits,
Vol24, No.5, October 1989.
This was the origin work of SONY Compact Digital CCD Image Sensor System Chipset.
Hagiwara was happy in the digital camera system team while SONY CCD top management
people suffered the large dark current related poor mass production technology problems.
The Interline Transfer CCD image sensor with tranparent electrode with the lateral
overflow drain had a serious problem of large dark current and very small light
window area because a large area was needed for the lateral overflow drain.
Hitachi had already MOS image sensor with the built-in vertical overflow drain(VOD).
NEC published in IEDM1982 the PNP junction type buried photodiode structure
in the Interline transfer CCD imager which has no image lag with the complete
charge transfer operation like the CCD type complete charge tranfer feature.
SONY CCD top management people finally decided to chage their target direction
and began to focus their dilligence on the P+NPNsub junction type photodiode
that was originally proposed persistantly by Hagiwara. Until then no one in Sony
understood the detailed features of Hagiwara invention and ignored Hagiwara.
SONY and Hagiwara himself suffered by SONY-Fairchild, SONY-NEC and SONY-
KODAK patent wars on the CCD image sensor patents of the SONY HAD sensor.
SONY-Fairchild patent war (1991-2000) finally ended and Sony won over Fairchild.
Finally Hagiwara became happy and began to appear in the public.
Hagiwara recieved three invitations from the international conferences for his works.
(12) "SONY Consumer Electronics" by Yoshiaki Hagiwara,
ESSCIRC2001 invited paper, at Vilach, Austria, September 2001
(13) "SOI Cell Processor and Beyond" by Yoshiaki Hagiwara,
ESSCIRC2008 invited paper, at Edinburgh, Scotland UK, September 2008
(14)The 60th Aniversary ISSCC2013 Plenary Panel Talk, by Yoshiaki Hagiwara,
at San Franicisco, USA, February 2013.
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SONYの萩原良昭が1975年に出願したPinned Photo Diode の発明特許以前の
固体撮像素子の開発研究に関する重要な学会発表論文リスト
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J.Bardeen and W.H.Brattain, "Transistor: A Semiconductor Triode",
Physical Review, VOl.74, p.230, July 1948.
W.Shockley, "The theory of p-n Junction in Semiconductor and p-n
Junction Transistor", Proc. IEEE Vol.51, pp.1190-1202, September 1949.
S.R.Hofstein and F.P.Heiman, "The Siliocn Insulated-Gate Field Effect
Transistor", Proc. IEEE Vol.51, pp.435-1202, September 1963
Gordon E. Moore, "Cramming more components onto integrated circits",
Electronics,
Vol.38, No.8, April 19, 1965.
M.A.Schuster and G.Strull, " A Monolithic Mosaic of Photo Sensors for Solid
State Imaging Application", IEEE Trans. Electron Devices, Vol.ED-13, No.12, 1966
A. S. Grove, “Physics and Technology of Semiconductor Devices,”
John Wiley and Sons, Inc., New York pp.136-140, no.267, 1967.
P.K.Wiener, et al "A self-Scanned Solid State Image Sensor", in Proc. IEEE,
Vol 55, No.9, 1967.
G.P.Weckler, "Operation of PN Junction Photo Detectors in a Photon Flux
Integrating Mode", IEEE J. Solid State Circuits. Vol2, pp.65-73, September 1967.
P.J.W. Noble, "Self-Scanned Silicon Image Dector Arrys", IEEE Trans. Electron
Devices, Vil.ED-15, No.4, pp.202-209,1968.
S.G. Chamberlain, "Photosensitivity and Scanning of Silicon Image Detector
Arrays" IEEE J.Solid State Circuits, Vol.SC-4, No.6, pp.333-342, 1969.
F.L.J.Sangster and K.Teer, "Bucket Brigate Electronics - New Possibilities
for Delay Time-Axis Conversion and Scanning", IEEE J.Solid-State Circuits,
VOl.SC-4, No.3, pp.131-136, 1969.
********* Important Mile Stones ******************
(1) W. S. Boyle and G. E. Smith,
“Charge-Coupled Semiconductor Devices,”
Bell Syst. Tech. J., 49, pp.587-593, 1970.
(2) Amelio, G. F., M. F. Tompsett, and G. E. Smith, 1970,
“Experimental verification of
the charge coupled device concept,”
Bell Syst. Tech. J. 49, 593.
(3) Michael Francis Tompsett at Bell Lab
U.S. Patent No. 4085456, Aug 30, 1972 by
(4) Boyle, W. S., and G. E. Smith, 1974,
“Buried channel charge coupled devices,”
U.S. Patent No. 3,792,322 February 12, 1974.
*********** Early Contributions in Japan ***********
(1) Yoshiaki Hagiwara ISSCC1974 Paper on
"Buried Channel CCD Charge Transfer"
February 1974 in Philadelphia, USA.
This was Hagiwara PhD thesis paper
at California Institute of Technology
(CalTech) Pasadena, California USA
under the PhD thesis guidance of
Prof. C.A. Mead and Prof. T.C. McGill
at Caltech, Pasadena in 1972 to 1975.
Hagiwara jointed Sony in Japan
on Februeary 20, 1975.
(2) Hagiwara at Sony filed on Oct 22, 1975
a Japanese Patents ( JP 1975-127647 )
on the NPN/Sub junction type Pinned Photodiode ,
with a built-in golobal shutter function using
a charge transfer gate also as the built-in global shutter
gate and also as a temporally MOS buffer capacitorance
next to the output charge tansfer device (CTD)
with the complete charge transfer operation mode
for very low image-lag action picture quality.
(3) Hagiwara at Sony filed on Nov 10, 1975
a Japanese Patent ( JP 1975-134985 )
on the NPN/Sub junction ( thyristor ) type
Pinned Photodiode structure
which is a combination of the P+NP junction type
Pinned Photodiode) with the NPNsub junction type
Vertical Overflow Drain (VOD) structure , which is
next to the output charge tansfer device (CTD)
with the complete charge transfer operation mode
for very low image-lag action picture quality.
This Pinned Photodiode is now also called as
the SONY original HAD sensor.
(3) Yamada at Toshiba filed in 1978 a Japanese
Patent ( JA 1978-1971 ) on Jan 13, 1978
on an NPNsub junction type Vertical Overflow
Drain (VOD1978) structure, which is a derivative
or duplicate patent of the Hagiwara 1975 invention
( JP 1975-134985 ) of the NPNsub junction type
Vertical Overflow Drain structure.
(4) Teranishi at NEC filed in 1980 a Japanese
Patent ( JA 1980-123259 ) on Oct 2, 1980
on an P+NPsub junction typePinned Photodiode
structure, which is a derivative or duplicate patent
of the Hagiwara 1975 invention ( JP 1975-134985 )
of the NPN/Sub junction type Pinned Photodiode.
SONY HAD ( Pinned Photodiode ) was perfected
by the following two works by Sony Engineers.
(5) K.Ishikawa and T.Iizuka, "One inch 2M pixel CCD
with Hyper HAD sensor and Camera System
for HDTV", SPIE proc. Vol. 1656, pp.30-40,
February 1992.
(6) K. Yonemoto and H. Sumi ,
"A CMOS Image Sensor with a Simple FPN
Reduction Technology and a Hole Accumulation
Diode", ISSCC2000, Dig.Tech.Papers,
pp.102-103, February 2000.
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W.M.Regitz and J.Karp, "A Three-transistor-cell, 1024 bit, 500 nsec
MOS RAM", ISSCC1970, Feb. 1970
F.L.J. Sanger, "Integrated MOS and Bipolar Analog Delay Lines using
Bucket Brigate Capacitor Storage", ISSCC1970, pp.74-75, 185, Feb. 1970.
G.F.Amelio, M.F.Tompsett and G.E.Smith, "Experimantal Verification of the
Charge Coupled Semiconductor Devices", B.S.T.J.Vol.49,pp.587-593,Apr. 1970
W.M.Regitz and J.Karp, "A Three-transistor-cell, 1024 bit, 500 nsec
MOS RAM", IEEE JSSC, VOl.SC-5, No.5, pp.181-186, October 1970.
W.F.Kosonocky and J.G.Carns, " Charge Coupled Digital Circuits", ISSCC1971,
pp.161-163, February 1971
G. F. Amelio, W. J. Bertram, Jr., and M. F. Tompsett,
“Charge-Coupled Imaging Devices: Design Considera- tions,”
IEEE Trans. Electron Devices, ED-18, no.11, pp.986-992, 1971.
M.F.Tompsett, et al "Charge Coupled Imaging Devces Experimental Results",
IEEE Trans. Electron Devices, Vol. ED-18, No.11, pp.992-996, 1971.
J.E.Carnes, "Drift-Aiding Fringing Fields in Charge Coupled Devices", IEEE J.
Solid State Circuits, Vol.SC-6, No.5, pp.322-326, 1971.
W.F.Kosonocky and J.G.Carns, " Charge Coupled Devices" ISSCC1972,
pp.132-133, February 1972.
C.H.Sequin, "Blooming Supression in Charge Coupled Area Imaging" Bell Sys.
Tech. J., 51, oo. 1923-1926, 1972.
J.D.Plummer and J.D.Meindl, " A Low-Light-Level Self-Scanned MOS Image
Sensor" ISSCC1972 Dig.Tech.Paper pp.30-31, February 1972.
J. E. Carnes and W. F. Kosonocky,
“First Interface-State Losses in Charge-Coupled Devices,”
Appl. Phys. Lett., vol.20, pp.261-263, 1972.
J. E. Carnes and W. F. Kosonocky,
“Noise Sources in Charge-Coupled Devices,”
RCA Review, vol.33, pp.327-343, 1972.
R. H. Walden, R. H. Krambeck, R. J. Strain, J. McKenna,
N. L. Schryer, and G. E. Smith, “The Buried Channel Charge
Coupled Devices,” Bell Syst. Tech. J., no.51, pp.1635-1640, 1972.
G. F. Amelio, “Physics and Applications of Charge Coupled Devices,”
IEEE INTERCON, New York, Digest, vol.6, paper 1/3, 1973.
D. M. Erb, W. Kotyczka, S. C. Su, C. Wang, and G. Clough,
“An Overlapping Electrode Buried Channel CCD,”
IEDM, Washington, D.C., Tech. Digest, pp.24-26, 1973.
W. F. Kosonocky and J. E. Carnes,
“Two Phase Charge Coupled Devices with Overlapping Polysilicon
and Aluminum Gates,” RCA Review, vol.34, pp.164-202, 1973.
D.M.Erb,W.Kotyczka, S.C. Su, C.Wamg and G.Clough, "An Overlapped
Electrode Buried Channel CCD", IEDM1973, Dec 3-5, 1973.
S. R. Shortes et al., “Development of a thinned backsideilluminated
charge-coupled device image,” in Proc. IEDM1973, Dec. 1973, p. 415.
N.G. Vogi, et al "A Half-Million Pel Bucket Brigate Optical Scanner",
ISSCC1974, pp. 30-31, February 1974.
P. A. Gray and H. Coltman, “Back surface imaging of thinned CCDs,”
in Proc. CCD, 1974, pp. 162–167.
J. Lohstroh, "The JFET as a Photosensitive Cell in Image Sensor Arrys",
ISSCC1974, pp. 34-35, February 1974.
M.H. White, "Characterization of Surface CHannel CCD Image Arrays at
Low Light Level", IEEE J. Solid State Circuits, Vol.SC-9, No.1, pp.1-12, 1974.
A. W. Lees and W. D. Ryan, “A Simple Model of a Buried-Channel
Charge-Coupled Device,” Solid-State Electron., vol.17, pp.1163-1169, 1974.
C. H. Sequin, F. J. Morris, T.A. Shankoff, M. F. Tompsett, and E. J. Zimany,
“Charge-Coupled Area Image Sensor Using Three Levels of Polysilicon,”
IEEE Trans. Electron Devices, ED-21, pp.712-720, 1974.
M. H. White, D. R. Lampe, F. C. Blaha, and I. A. Mack,
“Characterization of Surface Channel CCD Imaging Arrays
at Low Light Levels,” IEEE Trans. Solid-State Circuits,
SC-9, pp.1-13, Feb. 1974.
D. F. Barbe, “Imaging Devices Using the Charge-Coupled Concept,”
Proc. IEEE, vol.63, no.1, pp.38-67, 1975.
C. H. Sequin and M. F. Tompsett, “Charge Transfer Devices,”
Academic, New York, 1975.
James M. Early ( Fairchild Camera and Instrument Corporation, USA ) "Charge
Coupled Device with Overflow Protection", USP 3896485, July 22, 1975.
Hagiwara had to protect his 1975 Japanese patent ( 1975-127647 )
on the P+NPNsub Junction (Thyristor ) type Light Detecting Picture
Cell Structure agaist this Fairchild Early USP 3896485 patent.
The SONY-Fairchild Patent War lasted from 1991 till 2000.
Finally, Sony won the Patent war over Fairchild. But during the
long period of 10 years, Hagiwara felt as if he was in Jail and
could not perform any important job tasks in Sony at all.
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SONYの萩原良昭が1975年に出願した
Pinned Photo Diode の発明特許に関する重要な学会関連技術発表リスト
**********************************************************************
Hagiwara ISSCC1974 Paper on "Buried Channel CCD Charge Transfer"
February 1974 in Philadelphia, USA. This was Hagiwara PhD thesis paper
at California Institute of Technology (CalTech) Pasadena, California USA>
Hagiwara, 1975 Japanese Patent ( JA 1975-127647 ) at SONY
on the Pinned Photo Diode with Back Light Illumination
Hagiwara, 1975 Japanese Patent ( JA 1975-134985 ) at SONY
on the Pinned Phodo Diode with Vertical Overflow Drain Function
C.A.Mead, R.D.Pashley,Lee D. Britton, Yoshiaki T.Daimon Hagiwara and
S.F. Sando, "128-Bit Multicomparator", J. Solid State Circuits, Vol.SC-11,
No.5, October 1976. This is important for intelligent image sensor systems.
Hagiwara, 1978 Solid State Semiconductor Device Conference Paper on
"Narrow Channel Frame Transfer CCD Image Sensor" at Tokyo, Japan
.
This is the first paper in the world reporting the P+NP type ( dynamic
PNP junction ( photo transistor ) type light detecting picture element
structure, which was later called as the Pinned Photo Diode.
Y. Daimon-Hagiwara, M. Abe, and C. Okada, “A 380Hx488V CCD imager
with narrow channel transfer gates,” Proceedings of the 10th Conference
on Solid State Devices, Tokyo, 1978; Japanese J. Appl. Phys., vol. 18,
supplement 18–1, pp. 335–340, 1979.
Hagiwara, CCD'79 invited paper on "SONY Image Sensor Efforts"
at Edinburgh, Scotland UK on SONY CCD image sensors.
Fumio Miyaji, Yasushi Matsuyama, Yoshikazu Kanaishi, Katsunori Senoh,
Takashi Emori and Yoshiaki Hagiwara, "A 25 nanosec 4 Mega bit CMOS
RAM with DYnamic Bot-Line Loads", ISSCC1989 and J.Solid State Circuits,
Vol24, No.5, October 1989. This wad for Cache SRAM memory for SONY
Compact Digital CCD Image Sensors.
Y. Hagiwara, “High-density and high-quality frame transfer CCD imager
with very low smear, low dark current and very high blue sensitivity,”
IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2122–2130, Dec. 1996.
Hagiwara, ESSCIRC2001 invited paper on "SONY Consumer Electronics"
at Vilach, Austria
Hagiwara, ESSCIRC2008 invited paper on "SOI Cell Processor and Beyond"
at Edinburgh, Scotland UK
Hagiwara, the 60th Aniversary ISSCC2013 Plenary Panel Talk,
at San Franicisco, USA
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SONYの萩原良昭が1975年に出願した
Pinned Photo Diode の発明特許に関する頃の、時代背景について。
**********************************************************************
この国際学会で萩原は1975年発明の Pinned Photo Diodeの構造を
説明し、CCDの超感度低案電流は萩原考案の光感知素子の特徴で
あり、CCD自体は金属電極があり光感知素子には不向きであると論じ
ています。しかし一般メディアはCCDが高感度だと誤解したままでした。
1978年の初夏でした。萩原1975年発明のPinned Photo Diode 搭載の
FT型CCD Image Sensor の一体化ビデオカメラをSONYは新聞発表。
盛田会長が自らNewYorkで、岩間社長が自らTokyoで、同時に、
Press Conference を開催し、多くの新聞・テレビ・雑誌記者の前で、
大きく、新しい民生用小型ビデオカメラの時代を宣言しました。
しかし、ここでも、盛田会長と岩間社長は一般メディアに対しては
全体としてCCD Video Camera が高感度であることには変わりが
ないことから、一般メディアはCCDが高感度だと誤解したままでした。
ソニーは、萩原設計の 2-chip型の Interline 方式のCCD image
sensor の商品化に成功し、全日空(ANA)のジャンボジェット機の
コックピットに搭載し、飛行機の離着陸時の様子を機内のビデオ
スクリーンで迫力ある、real time の映像を見ることができました。
この 2-chip型の Interline 方式のCCD image sensor は 透明
電極を使用し、横型OFD構造でした。受光部は透明電極を使用
したCCD型の光感知素子構造を採用しており、CCDの完全空乏化
電荷転送により残像のない、Interline 方式のCCD image sensor
をSONYは既に1980年に実用化してビデオカメラに搭載しています。
その成果は国内学会でのみの発表が許可されました。
狩野、安藤、松本、萩原、橋本、 ”インターライン転送方式CCD撮像素子”
テレビジョン学会、電子装置研究会 ED 481, pp.47-52, Jan 24, 1980.
SONYの開発部隊は総力をあげて、この残像なしの、インターライン転送
方式CCD撮像素子の One Chip 化に取り組んでいました。
同時に、萩原1975年発明の Pinned Photo Diode の光感知素子
構造も、萩原1975年特許の中で説明している様に、CCDでなくても、
このPinned Photo Diode の光感知素子構造も、完全空乏化電荷
転送により残像がありません。かつ、光感度はCCD型よりもはるかに
超感度です。CCD型では、シリコン界面に強い電界がかかり、表面
再結合準位の存在の為に、CCD型では表面結合の暗電流が多い
でしたが、この萩原1975年発明の Pinned Photo Diode の光感知
素子構造では、表面は外部から電圧固定(ピン止め)されていて
電界がかからず、表面再結合準位が不活性(quench)され、表面
再結合による暗電流がありません。また表面捕獲準位の影響も
受けず、 trap 雑音、 1/f 雑音もない、超感度で低雑音を実現
しています。
ソニーは、当初から本命とされ、萩原が設計を担当し、その後、後輩の
竹下さんがその技術技術を継承した、 One chip の Interline 方式の
CCD Image Sensorの開発生産技術と信頼性技術に全力を注ぎました。
そして、世界発のPassportサイズの小型ビデオカメラの試作生産販売を
成し遂げました。ビデオカメラの市場を制覇、独占しました。
萩原1975年発明の、この高性能光感知素子構造が CCD Image Sensor
欠点を助け、CCDの延命に長く寄与しました。そして、その勢いは現在も継続し、
SONY Brand 商標の SONY original HAD sensor 搭載の CMOS Image
Sensor の技術力と生産力の基礎となっています。
さらに裏面照射型のPinned Photo Diode は、1975年萩原がこの特許の中で
世界で初めて構想していたもので、現在の「賢い電子の目」の実現の源点です。
Hagiwara, CCD'79 invited paper on "SONY Image Sensor Efforts"
at Edinburgh, Scotland UK on SONY CCD image sensors.
この国際学会で萩原は1975年発明の Pinned Photo Diodeの構造を
説明し、CCDの超感度低案電流は萩原考案の光感知素子の特徴で
あり、CCD自体は金属電極があり光感知素子には不向きであると論じ
ています。しかし一般メディアはCCDが高感度だと誤解したままでした。
この開発研究チームは国内の学会でその詳細を発表しています。
平田、大津、阿部、萩原、 "2/3 inch 狭チャンネルCCD撮像素子", テレビジョン
学会、テレビジョン方式・回路研究会 TEBS69-3, 電子装置研究会 ED 555,
pp.13-18, Feb. 27, 1981.
島田、梶野、西村、小室、中田、南、"狭チャンネルFT型CCDによる単板カラー
カメラ",テレビジョン学会、テレビジョン方式・回路研究会 TEBS70-4, Sept.8, 1981.
Hagiwara, ESSCIRC2001 invited paper on "SONY Consumer Electronics"
at Vilach, Austria
Hagiwara, ESSCIRC2008 invited paper on "SOI Cell Processor and Beyond"
at Edinburgh, Scotland UK
Hagiwara, the 60th Aniversary ISSCC2013 Plenary Panel Talk,
at San Franicisco, USA
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CCDの開発商品化を世界の多くの企業が断念し諦める中、SONYは世界で一社のみで
"Never Give Up " の精神で独走していました。その成果はSONYの次の国内論文の嵐
を引き起こしました。
ます、1978年のSONYの一体化ビデオカメラの発表が最初の花火でした。
その技術内容は東京で開催の国際固体素子コンファレンス1979年でまず
世界に紹介されました。
Y. Daimon-Hagiwara, M. Abe, and C. Okada, “A 380Hx488V CCD imager
with narrow channel transfer gates,” Japanese J. Appl. Phys., vol. 18,
supplement 18–1, pp. 335–340, 1979.
そして、萩原は、その発明開発技術者として、 Scotland UK の Edinburgh 大学で
開催の、CCDの国際会議 CCD79に、招待講演の招待を受けました。
Hagiwara, CCD'79 invited paper on "SONY Image Sensor Efforts"
at Edinburgh, Scotland UK on SONY CCD image sensors.
その後、SONYはさらに次々とCCDの開発成果を発表しました。
狩野、安藤、萩原、橋本、”インターライン転送方式CCD撮像素子”、
テレビジョン学会、電子装置研究会 ED481、pp. 47-52、Jan 24, 1980
名雲、山中、越智、”CCD カラーカメラの線順次撮像方式と信号処理方式”、
テレビジョン学会技術報告書 TEBS 60-1, pp. 19-25, Jan 25, 1980
村田、名雲、中田、安井、西村、小室、粂沢、”線順次 2CCDカラーカメラ”、
テレビジョン学会、テレビジョン方式・回路研究会 TEBS 60-2, pp. 27-32, Jan 25, 1980
この3つの国内論文の技術内容は国際学会にも以下の2つの論文の形でも発表されました。
F.Nagumo, T.Asada and S.Ochi, " CCD Digital Color Camera ", IEEE
Transaction
on Consumer Electronics, VOL.CE-26, No.8, pp. 339-352, Aug. 1980.
T.Asada and F.Nagumo, " A New Digital CCD Color Camera using Direct Encoding
Method", International Conference on Digital Signal Processing " Florence, Italy,
September 2 - 5 , 1980.
また、同時に構内では、やっと社内で One chip CCD カメラの
実際の技術開発者による、技術詳細の発表の許可がおりました。
平田、大津、阿部、萩原、 "2/3 inch 狭チャンネルCCD撮像素子", テレビジョン
学会、テレビジョン方式・回路研究会 TEBS69-3, 電子装置研究会 ED 555,
pp.13-18, Feb. 27, 1981.
島田、梶野、西村、小室、中田、南、"狭チャンネルFT型CCDによる単板カラー
カメラ",テレビジョン学会、テレビジョン方式・回路研究会 TEBS70-4, Sept.8, 1981.
しかし、その成果は会社全体の業績として、会社での開発TOP管理責任者の
実績として記録されることになりました。萩原をはじめ多くの萩原を支援して
くれた技術者陣が総力で成し遂げた仕事の成果実績を、会社のTOの森尾さん
と越智さんにピンはねされた瞬間でした。
”SONYの森尾、越智、土井の3氏にエドアルドライン賞”、毎日新聞、9月8日、1981.
実際には、以下の2つの仕事にも、萩原の開発した Image Sensorが搭載され、
採用されていますが、萩原とその協力技術者の業績の引用(citation) は皆無です。
”フィルム不要のカメラ 磁気ディスクで50枚撮れる、プリントOKカメラ屋さん脅威、
ソニーが開発”、読売新聞、8月25日、1981.
J. Marcom Jr. "Sony unveils a Camera that Doesn't Use Film",
Asian
Wall Street Journal, August 26, 1981.
木原、斎藤、浦原、中田、岡本、中鉢、”マビカシステム”、テレビジョン学会技術
報告 TEBS 80-5 , VR 50 - 5, pp. 25-31, March 25, 1981 .
その後、SONYは、萩原のオリジナル設計のCCD Image Sesnor を採用した、
マビカの商標名でデジタルマビカを商品展開し、市場を驚かせた。
実は、そのマビカの商標名の名づけの親は萩原自身だった。
当時、萩原がSONYの中研時代に、商品名称の社員公募があった時、萩原が、
Magnetic Video Camera を略して、MAVICAと命名し、応募し、偶然にも、それが
採用された事実がある。萩原はたいへん喜んだ。
たいへん偶然の、名誉あることだと萩原は感じた。その事は公募作業担当者以外、
まったく誰にも知られないことであった。しかし、萩原はSONYのデジタルマビカの
大の愛好者で、海外出張の時には必ず持って出かけた。母校のCalTechを訪問し、
恩師の Prof. T.C. McGIll や、 Prof. C.A. Mead も、大の愛好家であることを
知り、萩原はたいへん満足で幸せな気分だった。♡
![](128_bit_comparator.JPG)
![](image68.jpg)
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SONYの萩原良昭が1975年に出願したPinned Photo Diode の発明特許以後の
固体撮像素子の開発研究に関する重要な学会発表論文リスト
**********************************************************************
Gilbert F. Amelio ( Fairchild Camera and Instrument Corporation, USA )
"Self Aligned CCD Element including Two Levels of Electrondes and
Method of Manufacture therefor" USP 3931674, Jan 13, 1976.
This Amelio patent (USP3931674) which was judged invalid by the prior
art of USP3745647 by Boleky and by IEDM1973 paper by D.M.Erb,
W.Kotyczka, S.C.Su, C.Wamg and G.Clough, "An Overlapped Electrode
Buried Channel CCD", IEDM1973, Dec 3-5, 1973.
T. Yamada, H. Okano, and N. Suzuki, “The Evaluation of Buried Channel Layer
in BCCD’s,” IEEE Trans. Electron Devices, ED-25, no.5, pp.544-546, 1978.
J. Hynecek, “Virtual phase CCD technology,” in Proc. IEDM1979, pp. 611–614,
Dec. 1979,
J.Nishizawa, et al, "Static Induction Transistor Image Sensors", IEEE Trans.
Electron Devices, Vol.ED-26, No.12, pp.1970-1977, 1979.
A. Furukawa, Y. Matsunaga, N. Suzuki, N. Harada, Y. Endo, Y. Hayashimoto, S. Sato,
Y. Egawa, and O. Yoshida, “An Interline Transfer CCD for A Single Sensor 2/3” Color
Camera,” IEDM, Washington, D. C., Tech. Digest, pp.346-349, 1980.
K.Hoshi, T.Suzuki, Y.Okubo and N.Isawa, "CZ Siliocn Crystal grown in Transverse
Magnetic Fields", 157th ECS Mtg Ext. Abstract, pp.811-813, May 1980.
T.Asada and F.Nagumo, "A New CCD Digital Color Camera using Direct Encoding
Method", Int. Conf. on Digital Signal Processing, September 2-5, 1981, Florence Italy.
Y. Ishihara, E. Oda, H. Tanigawa, N. Teranishi, E. Takeuchi, I. Akiyama, K. Arai,
M. Nishimura, and T. Kamata, “Interline CCD Image Sensor with an Anti Blooming
Structure,” ISSCC Digest of Technical Papers, pp.168-169, Feb. 1982.
N. Teranishi, A. Kohno, Y. Ishihara, E. Oda, and K. Arai, “No Image Lag Photodiode
Structure in the Interline CCD Image Sensor,” IEDM Tech. Dig., pp.324-327, 1982.
Y.Ishihara and K.Tanigaki,"A High Photosensitivity IL-CCD Image Sensor with
Monolithic Resin Lens Array", IEDM1983 Tech. Dig, pp.497-500, December 1983.
B.C. Burkey et al, "The Pinned Photo Diode for an Interline Transfer Image Sensor",
IEDM1984, DIg.Tech.Papers, pp.28-31, December 1984.
K. Horii, T. Kuroda, and S. Matsumoto, “A New Configuration of CCD Imager with a
Very Low Smear Level -FIT-CCD Imager,” IEEE Trans. Electron Devices, ED-31, no.7,
pp.904-909, 1984.
Y. Matsunaga and N. Suzuki, “An Interline Transfer CCD Imager,” ISSCC Digest of
Technical Papers, pp.32-33, Feb. 1984.
M.Ogawa et al, "Signal-PRocesiing ICs employed in a Single-Chip CCD Color Camera",
IEEE TRansaction on Consumer Electronics, Vol.CE-30, No.3, pp.374-381, Aug.1984
T.Kumezawa et al, "High Resolution CCD Image Sensors with Reduced Smear", IEEE
transaction on Electron Devices, VOl. ED-32, No.8, pp.1451-1456,1618, Aug. 1985.
Y.Ogawa et al, "Development of CCD Imaging Block for Single Chip Color Camera",
IEEE Transaction on Consumer Electronics, Vol.CE-31, No.3, pp.405-413, Aug. 1985
T.Nakamura,"A New MOS Image Sensor Operating in a Non-destructive Readout
Mode", IEDM1986, Tech.Dig. pp.353-356, December 1986.
M.Yamamura et al, "A 1/2 inch CCD Imager with 510 x 492 pixels", SPIE Vol.765
Image Sensors and Displays pp.41-46, Jan 13-14, 1987.
T. Yamada, K. Ikeda, and N. Suzuki, “A Line-Address CCD Image Sensor,”
ISSCC Digest of Technical Papers, pp.106-107, Feb. 1987.
T. Yamada, T. Yanai, and T. Kaneko, “2/3 Inch 400,000 Pixel CCD Area Image Sensor,”
Toshiba Review, no.162, pp.16-20, Winter 1987.
N. Teranishi and Y. Ishihara, “Smear Reduction in the Interline CCD Image Sensor,”
IEEE Trans. Electron Devices, ED-34, no.5, pp.1052-1056, 1987.
A.J.P.Theuwissen et al, "A 400K Pixel 1/2 inch Accorion CCD Imager", ISSCC1988,
Dig.Tech.Papers, pp.48-49, February 1988.
M. Hamasaki, T. Suzuki, Y. Kagawa, K. Ishikawa, M. Miyata, and H. Kambe,
“An IT-CCD Imager with Electronically Variable Shutter Speed,” ITEJ Technical
Report, vol.12, no.12, pp.31-36, 1988.
H.Yamashita et al, "A New High Sensitivity Photo-transitor for Area
Image Sensors", IEDM1988 Tech Dig pp.353-356, December 1988.
J.Hynecek, "A New Device Architecture Suitable for High-Resolution
and High Performance Image Sesnors", IEEE Trans, Electron Devices,
Vol.35, No.5, pp.646-652, 1988.
N.Tanaka, et al,"A Novel Bipolar Imaging Device with Self-NOise Reduction
Capability", IEEE Trans. Electron Devices, Vol.36, No.1, pp.31-38, 1989
K.Yonemoto et al, "A 2 million Pixel FIT-CCD Image Sensor for HDTV
Camera System" IEEE ISSCC1990, pp.214-216, February 1990.
F.Andoh et al,"A 250 000 Pixel Image Sensor with FET Amplification
at Each Pixel for High Speed Television Cameras", ISSCC1990, Dig.Tech.Papers
pp.212-213, February 1990.
Eric G. Stevens et al, "A One Mega Pixel Progressive Scan Image Sensor with
Antiblooming Control and Lag-Free Operation", IEEE Trans. Electron Devices,
Vol38, No.5, pp.981-988, 1991.
K.Ishikawa and T.Iizuka, "One inch 2M pixel CCD with Hyper HAD sensor and
Camera System for HDTV", SPIE proc. Vol. 1656, pp.30-40, February 1992.
T. Ishigami, A. Kobayashi, Y. Naito, A. Izumi, T. Hanagata, and K. Nakashima,
“A 1/2-in 380k-pixel Progressive Scan CCD Image Sensor,” ITE Technical Report
Vol.17, no.16, pp.39-44, Mar. 1993.
P.B.Denyer et al, "CMOS Image Sensors for Multimedia Applications", IEEE
Constum Integrated Circuits Conference 1993, Proc. of CICC1993,
pp.11.5.1-11.5.4, 1993.
H.Kawashima et al, "A 1/4 inch Format 250K Pixel Amplified MOS Image Sensor
Using CMOS Process", IEDM1993, Tech. Dig. pp.575-578, December 1993.
S.K.Mendis et al, "128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated
Imaging Systems", IEDM1993, Tech. Dig. pp.583-586, December 1993.
E.R.Fossum,"Active Pixel Sensors: Are CCD's dinosaurs ?" , in Proc. SPIE,
Vol.1900, pp.2-14, 1993.
Hitachi MOS Image Sensor Engineers and Intel MOS Process
Engineers all knew that eventually the scaled down MOS Process
Technology will conquer all other kinds of Process Technologies
including CCD image sensor technology, because of the power
consideration and scaled down dimensional advantage of CMOS
process technology.
The three transistor CMOS active picture cell was already
invented as, since the three-transistor circuit is identical to,
the three-transitorcircuit of the DRAM cell, with the active
source follower type current amplification.
Fossum was just a commentator in his SPIE 1993 paper above,
emphasizing the fact and speculations that the original image
sensor experts and engineers all knew in 1970s.
Fossum did not the develop the compact digital CMOS image
sensors. Sony delligent engineering team did. Fossum was
just a commentator on the well known speculations.
R.H.Nixon et al, "128 x 128 CMOS Photodiode Type Active Pixel Sensor
with On-ChipTiming Ccntrol and Signal CHain Electronics", in Proc. SPIE,
Vol.2415, pp.117-123, 1995.
S. Kawai et al, "Photo Response Analysis in CCD Image Sensors with a VOD
Structure", IEEE TRans. Electron Devices, VOl.42, No.4, pp.652-655, 1995.
Paul P. K. Lee et al, "An Active Pixel Sensor Fabricated Using CMOS/CCD
Process Technology", in Proc. IEEE Workshop on CCDs and Advanced
Image Sesnors", 1995.
S.Kawahito et al,"A Compressed Digital Output CMOS Image Sensor with
Analog 2-D DCT Processors and ADC/Quantizer",ISSCC1997, Dig.Tech.Papers,
pp.184-185, February 1997.
T. H. Lee, R. M. Guidash, and P. P. Lee, “Partially pinned photodiode
for solid-state image sensors,” U.S. Patent 5,903,021, Jan. 1997.
R. M. Guidash, “Active pixel image sensor with shared amplifier
readout,” U.S. Patent no. 6,107,655, Aug. 1997.
Walter F. Kosonocky et al, "360 x 360 Element Three-Phase Very High
Frame Rate Burst Image Sesnor, Design, Operation and Perfomance",
IEEE Trans. Electron Devices, Vol.44, No.10, pp.1617-1624, 1997.
R.M.Guidash et al, "A 0.6 um CMOS Pinned Photo Diode Color Imager
Technology", IEDM1997, Tech. Dig. pp.927-929, December 1997.
M.Loinaz, et al, "A 200mW 3.3V CMOS Color Camera IC Producing
352 x 288 24b Video at 30 Frames/sec", ISSCC1998, Dig.Tech.Papers,
pp.168-169, February 1998.
Guang Yang, Orly Yadid-Pecht, Chris Wrigley, and Bedabrata Pain ,
"A Snap-Shot CMOS Active Pixel Imager for Low-Noise, High-speed
Imaging", IEDM1998, December 1998.
F.Andoh et al, "A Digital Pixel Image Sensor with 1 bit ADC and
8 bit Pulse Counter in Each Pixel", International Image Sensor
Workshop, P1, 1999.
K. Yonemoto and H. Sumi , "A CMOS Image Sensor with a Simple FPN
Reduction Technology and a Hole Accumulation Diode", ISSCC2000,
Dig.Tech.Papers, pp.102-103, February 2000.
T. Yamada, Katsumi Ikeda, Y. G. Kim, H. Wakoh, T. Toma, T. Sakamoto,
K. Ogawa, E. Okamoto, K. Masukane, K. Oda, and M. Inuiya, “A progressive
Scan CCD Image Sensor for DSC Applications,” IEEE J. of Solid-State
Circuits, vol.35, no.12, pp.2044-2054, 2000.
M.Furuyama et al,"High Sensitivity and No Crosstalk Pixel Technology
for Embedded CMOS Image Sesnor", IEEE Trans. Electron Devices,
Vol.48, No.10, 2001.
T.Miida,"A 1.5 M Pixel Imager with Localized Hole-Modulation Method",
ISSCC2002, Dig.Tech.Papers, pp.42-43, February 2002.
T. GOji Etoh,"A CCD Image Sensor of 1Mframe/sec for Continuous
Image Capturing 103 Frames", ISSCC2002, Dig.Tech.Papers, pp.46-47,
February 2002.
T.Sugiyama et al, "A 1/4 inch QVGA Color Imaging and 3-D Sensing
CMOS Sensor with Analog Frame Memory", ISSCC2002,Dig.Tech.Papers,
pp.434-435, February 2002.
A. Theuwissen, "50 years of Solid State Image Sensors",
ISSCC2003, Dig.Tech. Papers, S26, February 2003.
I. Inoue et al., “Low-leakage-current and Low-operating-voltage
Buried Photodiode for a CMOS imager,” IEEE Trans. Electron Devices,
vol. 50, no. 1, pp. 43–47, Jan. 2003.
K.Mabuchi,N.Nakamura, E.Funatsu,T.Abe,T.Umeda,T.Hoshino,R.Suzuki,
H.Sumi, "CMOS Image Sensor Using a Floating Diffusion Driving Buried
Photo Diode", ISSCC2004, pp.112-113, February 2004.
H.Takahashi et al, "A 3.9 um Pixel Pitch VGA Format, 10 bit Digital
Image Sensor with 1.5 Transistor /Pxcel", ISSCC2004, pp.108-109, Feb. 2004.
M.Mori et al, "A 1/4 inch 2M Pixel CMOS Image Sensor with 1.75
Transistor/Pixel", ISSCC2004, pp.110-111, February 2004.
Nana Akahane, Rie Ryuzaki, Satoru Adachi, Koichi Mizobuchi,
Shigetoshi Sugawa, "A 200dB Dynamic Range Iris-less CMOS Image
Sensor with Lateral OverflowIntegration Capacitor using Hybrid Voltage
and Current Readout Operation", ISSCC2006, pp.300-301, Feb.7, 2006.
Shin Iwabuchi et al,"A Back illunated High Sensitivity Small Pixel
Color CMOS Image Sensor with Flexible Layout of Metal Wiring",
ISSCC2006, pp.302-303, Feb.7, 2006
Y. Nitta et al, "High Speed Digital Double Sampling with Analog CDS
on Column parallel ADC Architecture for Low Noise Active Pixel Sensor",
ISSCC2006, pp.500-501, Feb. 8, 2006
S.Yoshihara et al, "A 1/1.8 inchi 6.4 Mega Pixel 60 frames/sec CMOS
Image Sensor with Seamless Mode Change", ISSCC2006, Dig.Tech.Papers
pp.1984-1993, February 2006.
Dr. A.J.P. Theuwissen、
“The Hole Role in Solid-State Imagers“
IEEE Transaction. Electron Devices,
Vol. ED-53, no. 12, pp. 2972-2980, 2006.
http://www.harvestimaging.com/pubdocs/101_2006_dec_TED_hole_role.pdf
![](Pinned_Photodiode_Patent_1975_by_Sony_Hagiwara_page001.jpg)
![](image209.jpg)
K.Cho et al, " A 1/2.5 inch 8.1 Mega Pixel CMOS Image Sesnor for
Digital Camera",ISSCC2007, Dig.Tech.papers pp.508-509, February 2007.
S-H Cho et al, "Optoelectronic Investigation for High Performance 1.4 um
pixel CMOS Image Sensors", International Image Sensor Workshop (IISW2007),
June 6-10, 2007.
Xinyang Wang, Padmakumar R.Rao, and Albert J.P. Theuwissen,
"Characterization of the Buried CHannel NMOS Source Followers
in CMOS Image Sesnors", International Image Sensor Workshop
(IISW2007), June 6-10, 2007.
Shoji Kawahito and Nobuhiro Kawai, "Column Parallel Signal
Processing Techniues for Reduing Thermal and RTS Noises in
CMOS Image Sensors", International Image Sensor Workshop
(IISW2007), June 6-10, 2007.
G.Agranov et al, "Super Small Sub 2 um Pixels for Novel CMOS
Image Sensors", International Image Sensor Workshop (IISW2007),
June 6-10, 2007.
J.Prima et al, "A 3 Mega Pixel Back illuminated Image Sensor
in 1T5 Architecture with 1.45 um Pixel Pitch", International
Image Sensor Workshop (IISW2007), June 6-10, 2007.
B.Cremers et al, "A High Speed Pipelined Snapshoto CMOS Image
Sensor with 6.4 Gpixel/sec Data Rate", International Image Sensor
Workshop 5.9, p.9, 2009.
K.Itonaga et al, "Extremely Low Noise CMOS Image Sensor
with High Saturation Capacity", IEDM2011, Dig.Tech.Papers
pp.171-174, December 2011.
M.Sakakibara et al,"An 83 dB Dynamic Range Single Exposure Global
Shutter CMOSImage Sensor with In-Pixek Dual Storage", ISSCC2012,
Dig.Tech.Papers, 22.1, pp.380-381, February 2012.
T.Tochigi et al, "A Global Shutter CMOS Image Sensor with Readout
Speed of One Tpixel/secBurst and 780 Mpixel/sec Continuous",
ISSCC2012, Dig.Tech.Papers, 22.1, pp.382-384, February 2012.
E.R.Fossum and D.B.Hondongwa, " A Review of the Pinned Photo Diode
for CCD and CMOS Image Sensors", IEEE J. of Electron Devices Society,
VOL-2, No.3, May 2014. This is a fake paper which did not quote the
Hagiwara 1975 patent on the Back Light Illuminated Pinned Photo Diode
Light Detecting Element Structure ( 1975-127647 ) with the complete
charge transfer operation mode with the image lag free feature. This
Fossum fake 2014 paper made also many false statements on the Hagiwara
1975 patent on the P+NPNsub junction (thysitor) type Pinned Photo Diode
Light Detecting Element Structure ( 1975-134985 ) that has the complete
charge transfer action with no image lag feature, and also with the built-in
vertical overflow drain (VOD) function.
Fossum is not the inventor of the active image sensor picture element.
Peter Noble is the inventor of the active image sensor picture element.
http://www.pjwn.co.uk/
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これは70歳じじいのぶつぶつぼやきの独り言でした。
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![](imageHagiwara01.jpg)
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The AIPS image sensor watching at its inventor, Yoshiaki Hagiwara.
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